Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices
US6855620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 2, 2001 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Mar 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0137
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth. Thereafter, the remaining GaN layer 31 is removed through etching, together with the GaN layer 32 formed atop the GaN layer 31, and subsequently, a GaN layer 33 is lateral-epitaxially grown with the top surfaces of mesas and sidewalls of trenches serving as nuclei, the mesas and trenches being formed of the remaining GaN layer 32, thereby producing a GaN substrate 30 in which threading dislocations are considerably suppressed. When the area of a portion …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.