Multi-chips stacked package
US6856027B2 · kind B2 · utility
4Cited by
3References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 9, 2004 |
| Grant date | Feb 15, 2005 |
| Priority date | — |
| Expiry date | Apr 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chips stacked package at least comprises a substrate, an upper chip, a lower chip, a plurality of electrically conductive wires and a plurality of conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate; and the lower chip is accommodated in the opening and wire-bonded to the upper chip. Furthermore, the lower chip can be wire-bonded to the substrate via a plurality of another electrically conductive wires, which directly connect the lower chip and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.