Method for adjusting the overlay of two mask planes in a photolithographic process for the production of an integrated circuit
US6858445B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Mar 12, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70633
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present invention provides a method for optimizing the overlay adjustment of two mask planes in a photolithographic process for the production of an integrated circuit having the following steps: provision of a substrate (S) with at least one first mask plane (ME), which has been patterned by exposure of a first mask using a first exposure device; orientation of a second mask (M), which is provided for the patterning of a second mask plane using a second exposure device, with respect to the first mask plane (ME); measurement of the overlay between the first mask plane (ME) and the second mask (M); analysis of the measured overlay taking account of error data (FAD, FXD, FBD, FYD) provided, in advance regarding errors (FA, FX, FB, FY) of the first and second masks and/or errors of the first and second exposure devices; carrying out of a correction of the orientation of the second mask (M) depending on the result of the analysis.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.