Method for testing semiconductor chips
US6858447B2 · kind B2 · utility
3Cited by
7References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 21, 2002 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | May 21, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/83
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing semiconductor chips, in particular semiconductor memory chips, is described. In which, in a chip to be tested, at least one test mode is set, the test mode is executed in the chip and test results are output from the chip. It is provided that, after the setting and before the performance of the test mode, a check mode is executed in which the status of the test mode set in the chip is read out in a defined format.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.