Semiconductor fabrication method for making small features
US6858542B2 · kind B2 · utility
12Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Feb 22, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.