Efficient ESD protection with application for low capacitance I/O pads
US6858902B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2003 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
Abstract
A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.