Back-to-back connected power semiconductor device package
US6858922B2 · kind B2 · utility
13Cited by
20References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2002 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Jan 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.