Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array
US6858941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2000 |
| Grant date | Feb 22, 2005 |
| Priority date | — |
| Expiry date | Dec 7, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chip stack structure and method of fabrication are provided utilizing self-aligning electrical contact arrays. Two or more arrays of interconnection contacts are provided, with one array being a rough aligned contact array, and a second array being a high bandwidth contact array. The rough aligned contact array has larger contacts and at least a portion thereof which melts at a substantially lower temperature than the melting temperature of the contacts of the high bandwidth contact array. By positioning two integrated circuit chips in opposing relation with the arrays mechanically aligned therebetween, and applying heat to melt the contacts of the rough aligned array, the two chips will rotate to align the respective contacts of the high bandwidth contact arrays, thereby achieving improved connection reliability between the structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.