Low-pin-count chip package and manufacturing method thereof
US6861295B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2001 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Dec 19, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low-pin-count chip package including a die pad for receiving a semiconductor chip and a plurality of connection pads electrically coupled to the semiconductor chip. The semiconductor chip, the die pad, and the connection pads are encapsulated in a package body such that the lower surfaces of the die pad and the connection pads are exposed through the package body. The present invention is characterized in that the die pad and the connection pads have a substantially concave profile thereby prolonging the time for moisture diffusion into the package as well as enhancing the “locking” of the die pad and the connection pads in the package body. The present invention further provides a method of producing the low-pin-count chip package described above.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.