Method of manufacturing a semiconductor integrated circuit device
US6861344B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2003 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | May 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The corrosion of a pad portion on TEG is prevented, and the wettability of a solder and the shear strength after solder formation of a pad portion of an actual device are improved. A third layer wiring M3 on a chip area CA of a semiconductor wafer and a third layer wiring M3 on a scribe area SA are respectively comprised of a TiN film M3a, an Al alloy film M3b, and a TiN film M3c. A second pad portion PAD2 as the top of a rewiring 49 on the chip area CA is cleaned. Alternatively, an Au film 53a is formed thereon by an electroles splating method. Further, after the formation of the Au film 53a, a retention test is carried out. Thereafter, further, an Au film 53b is formed and a solder bump electrode 55 is formed. As a result, it is possible to prevent the corrosion of a first pad portion PAD1 of the third layer wiring M3 on the scribe area SA which is TEG due to a plating solution or the like by the TiN film M3c. Further, it is possible to improve the wettability of a solder and the shear strength after solder formation of the second pad portion PAD2 by the Au films 53a and 53b.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.