Double-sided polishing process for producing a multiplicity of silicon semiconductor wafers

US6861360B2 · kind B2 · utility

Assignee

• Siltronic AG · DE

Inventors

• Guido Wenski · Burghausen, DE
• Thomas Altmann · Burghausen, DE
• Anton Huber · Burghausen, DE
• Alexander Heilmaier · Haiming, DE

Key dates

• Filing date: Nov 14, 2002
• Grant date: Mar 1, 2005
• Expiry date: Nov 14, 2022

Classification

• Technology area (CPC B): Performing Operations; Transporting
• CPC primary: B24B49/16
• WIPO field: Machine tools
• WIPO sector: Mechanical engineering

Abstract

A silicon semiconductor wafer with a diameter of greater than or equal to 200 mm and a polished front surface and a polished back surface and a maximum local flatness value SFQRmax of less than or equal to 0.13 μm, based on a surface grid of segments with a size of 26 mm×8 mm on the front surface, wherein the maximum local height deviation P/V(10×10)max of the front surface from an ideal plane is less than or equal to 70 nm, based on sliding subregions with dimensions of 10 mm×10 mm. There is also a process for producing a multiplicity of silicon semiconductor wafers by simultaneous double-side polishing between in each case one lower polishing plate and one upper polishing plate, which rotate, are parallel to one another and to which polishing cloth has been adhesively bonded, while a polishing agent, which contains abrasives or colloids, is being supplied, with at least 2 μm of silicon being removed, wherein a predetermined proportion of the semiconductor wafers is at least partially polished using a lower polishing pressure, and a further proportion of the semiconductor wafers is polished using a higher polishing pressure.