Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration

US6861688B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Dirk Manger · Dresden, DE
• Till Schlosser · Dresden, DE

Key dates

• Filing date: Nov 5, 2002
• Grant date: Mar 1, 2005
• Expiry date: Apr 16, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/482

Abstract

A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2 structures.