One transistor DRAM cell structure and method for forming
US6861689B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Mar 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldPharmaceuticals
- WIPO sectorChemistry
Abstract
A single transistor DRAM cell is formed in a SOI substrate so that the DRAM cells are formed in bodies that are electrically isolated from each other. Each cell has doped regions that act as source and drain contacts. Between the drain contact and the body is a region, which aids in impact ionization and thus electron/hole formation during programming that is the same conductivity type as the body but of a higher concentration than the body. Adjacent to the source contact and to the body is a region, which aids in diode current during erase, that is the same conductivity type as the source contact but of a lower concentration than the source contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.