Wafer level chip size package having rerouting layers
US6861742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2002 |
| Grant date | Mar 1, 2005 |
| Priority date | — |
| Expiry date | Jan 20, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.