Determination of nonphotolithographic wafer process-splits in integrated circuit technology development
US6864107B1 · kind B1 · utility
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10Claims
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Key dates
| Filing date | Jun 11, 2003 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | Sep 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system of testing wafer process-splits in a semiconductor wafer is provided. A first test is performed on a semiconductor wafer in a plurality of locations to obtain first data. The first data is clustered into a plurality of bins to obtain process-split locations. Second tests are performed on the semiconductor wafer in the process-split locations to obtain second data. The first data and second data arc correlated to determine process-split data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.