Method of producing large-area membrane masks by dry etching
US6864182B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2002 |
| Grant date | Mar 8, 2005 |
| Priority date | — |
| Expiry date | May 31, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/942
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Based upon an existing or to be produced multi-layered semiconductor-insulator-semiconductor carrier layer wafer (SOI substrate), irregularity of the etching conditions between the center and the edge region occurring during dry etching can be counteracted by a number of alternative steps, in particular, an additional layer construction compensating for the etching irregularity so that in any event an approximately homogeneous etching removal takes place over the entire area of the wafer to be etched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.