Formation of dual work function gate electrode
US6867087B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2001 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Nov 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0177
Abstract
In a method of making a dual work function gate electrode of a CMOS semiconductor structure, the improvement comprising formation of the dual work function gate electrode so that there is no boron penetration in the channel region and no boron depletion near the gate oxide, comprising:a) forming a gate oxide layer over a channel of a nMOS site and over a channel of a pMOS site;b) forming an undoped polysilicon layer over the gate oxide layer;c) masking the pMOS site, forming an a-Si layer over the nMOS site using a first heavy ion implantation, and implanting arsenic solely into the a-Si layer;d) masking the nMOS site formed by step c), forming an a-Si layer over the pMOS site using a second heavy ion implantation, and implanting boron solely into the a-Si regions;e) laser annealing the nMOS and pMOS sites for a short time and at an energy level sufficient to melt at least a portion of the a-Si but insufficient to melt the polysilicon; andf) affecting cooling after laser annealing to convert a-Si into polysilicon without gate oxide damage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.