Semiconductor integrated circuit device and its manufacturing method
US6867123B2 · kind B2 · utility
59Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2001 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Nov 30, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer which has finished formation of a relocating wiring layer thereon is stored and after determination of a design, solder bumps are formed over bump lands (one end of the relocating wiring layer) in accordance with a pattern which differs with a design, whereby a function or characteristic depending on the design is selected. The semiconductor wafer is then cut into a plurality of semiconductor chips, whereby a wafer level CSP is available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.