Stack chip module with electrical connection and adhesion of chips through a bump for improved heat release capacity
US6867486B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 18, 2001 |
| Grant date | Mar 15, 2005 |
| Priority date | — |
| Expiry date | Dec 18, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack chip module includes a substrate having a predetermined-size groove on one side and a circuit pattern, one end of the circuit pattern being adjacent to the groove; a first semiconductor chip adhered in the groove of the substrate by adhesive and having a plurality of center pads and a plurality of edge pads, electrically connected to each other, on the upper part thereof; a plurality of gold wires for electrically connecting the circuit pattern of the substrate and the edge pads of the first semiconductor chip, respectively; a second semiconductor chip having a plurality of center pads corresponding to those of the first semiconductor chip, the formative side being opposite to that of the first semiconductor chip; and a plurality of bumps interposed between the center pads of the first semiconductor chip and the center pads of the second semiconductor chip for joining and electrically connecting them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.