Process for manufacturing a semiconductor wafer integrating electronic devices including a structure for electromagnetic decoupling
US6869856B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 29, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Oct 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.