Method to achieve STI planarization

US6869857B2 · kind B2 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Feng-Wei Dai · Beijing, CN
• Pang Choong Hau · Singapore, SG
• Peter Hing · London, GB
• Lap Chan · San Francisco, US

Key dates

• Filing date: Nov 30, 2001
• Grant date: Mar 22, 2005
• Expiry date: Mar 19, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31056
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A new method of forming shallow trench isolations without using CMP is described. A plurality of isolation trenches are etched through an etch stop layer into the semiconductor substrate leaving narrow and wide active areas between the trenches. An oxide layer is deposited over the etch stop layer and within the trenches using a high density plasma chemical vapor deposition process (HDP-CVD) having a deposition component and a sputtering component wherein after the oxide layer fills the trenches, the deposition component is discontinued while continuing the sputtering component until the oxide layer is at a desired depth. In one method, the oxide layer overlying the etch stop layer in the wide active areas is etched away. The etch stop layer and oxide layer residues are removed to complete planarized STI regions. In another method, a second etch stop layer is deposited over the oxide layer using a HDP-CVD process whereby the second etch stop layer is sputtered away over the oxide layer overlying the first etch stop layer in the narrow active areas and whereby the second etch stop layer remains in the wide active areas. The second etch stop layer over the oxide layer in the wide act…