Power switching transistor with low drain to gate capacitance
US6870221B2 · kind B2 · utility
4Cited by
14References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 9, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Dec 9, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A transistor (10) is formed on a semiconductor substrate (12) with a first surface (19) for forming a channel (40). A gate dielectric (22) has a first thickness overlying a first portion of the channel, and a dielectric film (20) overlies a second portion of the channel and has a second thickness greater than the first thickness. The second thickness reduces the drain to gate capacitance of the transistor, thereby improving its switching speed and frequency response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.