Patent · US Expired

Circuit configuration and method for assessing capacitances in matrices

US6870373B2 · kind B2 · utility

1Cited by

1References

49Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ute Kollmer · Munich, DE
Stephan Sauter · Munich, DE
Carsten Linnenbank · Munich, DE
Roland Thewes · Puchheim, DE

Key dates

Filing date	Sep 6, 2002
Grant date	Mar 22, 2005
Priority date	—
Expiry date	Aug 21, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/063
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A circuit configuration for assessing capacitances in a matrix, which has a number of rows with at least one capacitance in at least one dimension, includes a test arm connected to first electrodes of each of the capacitances to be assessed and by which two different potentials can be applied to the first electrodes, a measurement arm connected to second electrodes of each of the capacitances to be assessed and that has a first measurement path and a second measurement path connected to a common potential. The first measurement path has an instrument for assessing the capacitances and the first and second measurement paths can be connected to the second electrodes. The circuit configuration has a drive device that connects each of the capacitances to be assessed individually to the two different potentials.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.