System and method for measuring a capacitance associated with an integrated circuit
US6870375B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2002 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Oct 2, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for measuring a capacitance associated with a portion of an integrated circuit is provided that includes coupling a measurement circuit to an integrated circuit. One or more transistors within the integrated circuit are initialized such that a steady-state associated with one or more of the transistors is achieved. A capacitance associated with the portion of the integrated circuit is then measured using the measurement circuit. The portion of the integrated circuit is selectively charged and discharged in response to a voltage potential being applied thereto such that a drain current is generated that serves as a basis for the capacitance measurement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.