Data transmission circuit for memory subsystem, has switching circuit that selectively connects or disconnects two data bus segments to respectively enable data transmission or I/O circuit connection
US6871253B2 · kind B2 · utility
110Cited by
11References
122Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2001 |
| Grant date | Mar 22, 2005 |
| Priority date | — |
| Expiry date | Mar 20, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and associated apparatus is provided for improving the performance of a high speed memory bus using switches. Bus reflections caused by electrical stubs are substantially eliminated by connecting system components in a substantially stubless configuration using a segmented bus wherein bus segments are connected through switches. The switches disconnect unused bus segments during operations so that communicating devices are connected in an substantially point-to-point communication path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.