Method of making a semiconductor chip assembly with a conductive trace and a substrate
US6872591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Aug 22, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4046
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a semiconductor chip assembly includes providing a semiconductor chip, a conductive trace and a substrate, wherein the chip includes first and second opposing major surfaces and a conductive pad, the pad extends to the first surface of the chip, the substrate includes first and second opposing major surfaces, a conductive terminal and a dielectric base, the conductive terminal extends through the dielectric base to the first and second surfaces of the substrate, a cavity extends from the first surface of the substrate into the substrate, the first surfaces of the chip and the substrate face in a first direction, the second surfaces of the chip and the substrate face in a second direction, and the chip extends into the cavity, and then electrically connecting the conductive terminal to the pad using the conductive trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.