Patent · US Expired

Process flow for dual damescene interconnect structures

US6872665B1 · kind B1 · utility

1Cited by
12References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 22, 2000
Grant dateMar 29, 2005
Priority date
Expiry dateJun 22, 2020

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76808
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.