Patent · US Expired

Test circuit arrangement and method for testing a multiplicity of transistors

US6873173B2 · kind B2 · utility

23Cited by

3References

11Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Ute Kollmer · Munich, DE
Ulrich Schaper · Munich, DE
Carsten Linnenbank · Munich, DE
Roland Thewes · Puchheim, DE

Key dates

Filing date	Mar 5, 2001
Grant date	Mar 29, 2005
Priority date	—
Expiry date	Mar 5, 2021

Classification

Technology area (CPC G)Physics
CPC primaryG11C2029/5004
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

The invention relates to a test circuit configuration. Every gate terminal of a transistor to be tested is coupled to a gate voltage source in such a manner that the gate voltage can be measured and adjusted individually on every gate terminal. The source terminal of every transistor to be tested can be coupled to the source voltage source in such a manner that the source voltage can be measured and adjusted individually on every source terminal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.