Memory device
US6873543B2 · kind B2 · utility
137Cited by
20References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2003 |
| Grant date | Mar 29, 2005 |
| Priority date | — |
| Expiry date | Oct 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a memory device. In one embodiment, the memory device comprises an array of memory cells configured to provide resistive states, a read circuit configured to sense the resistive states and a resistor. The resistor is configured to provide a resistance to the read circuit that is configured to select the resistor and sense the resistance to test the read circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.