Method of manufacturing high coupling ratio flash memory having sidewall spacer floating gate electrode
US6875660B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | May 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer. A tunneling oxide layer is formed over the substrate and then a first spacer is formed on the sidewall of the first conductive layer. Thereafter, a second conductive layer is formed on one side designated for forming a source region of the sidewalls of the first gate structure and the second gate structure. Then, the source region is formed in the substrate in the designated area. Next, an inter-gate dielectric layer is formed over the second conductive layer and then an insulating layer is formed over the source region. After forming a third conductive layer over the area between the first gate structure and the second gate structure, a drain region is formed in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.