Method for patterning multilevel interconnects
US6875699B1 · kind B1 · utility
4Cited by
6References
13Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 1, 2002 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Aug 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a damascene structure above a substrate is provided. A low-k dielectric layer is formed over the substrate, wherein the low-k dielectric layer does not have a trench stop layer. A plurality of vias are etched through the low-k dielectric layer. Via plugs are formed in the plurality of vias. A plurality of trenches are etched into the low-k dielectric layer, wherein the etching with sufficiently high via plugs minimizes facet formation at the tops of vias exposed to the etch and wherein the trench etch process removes fences caused by the via plugs. The via plugs are stripped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.