Method of forming a metal-insulator-metal capacitor structure in a copper damascene process sequence
US6876027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2003 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Aug 5, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/692
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a metal-oxide-metal (MIM), capacitor structure wherein the fabrication procedures used for the MIM capacitor structure are integrated into a process sequence used to form damascene type copper interconnect structures for CMOS type devices, has been developed. The process sequence features a copper damascene connector located overlying exposed portions of a semiconductor substrate, and underlying the MIM capacitor structure. The MIM capacitor structure, comprised a capacitor dielectric layer sandwiched between conductive capacitor plates, is protected during several selective reactive ion etching patterning procedures by an overlying anti-reflective coating (ARC), insulator shape, and by insulator spacers located on the sides of the ARC shape and on the sides of a capacitor dielectric shape. The presence of the insulator shape protects the MIM capacitor structure during a subsequent process used to define another copper damascene connector structure, overlying and contacting the MIM capacitor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.