Method and apparatus for split gate source side injection flash memory cell and array with dedicated erase gates
US6876031B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 23, 1999 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Feb 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transistor structure having a dedicated erase gate where the transistor can be used as a memory cell is disclosed. The presently preferred embodiment of the transistor comprises a floating gate disposed on a substrate and having a control gate and an erase gate overlapping said floating gate, with drain and source regions doped on the substrate. By providing a dedicated erase gate, the gate oxide underneath the control gate can be made thinner and can have a thickness that is conducive to the scaling of the transistor. The overall cell size of the transistor remains the same and the program and read operation can remain the same. Both the common source and buried bitline architecture can be used, namely twin well or triple well architectures. A memory circuit using the transistors of the present invention is disclosed as well for flash memory circuit applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.