Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6877086B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2000 |
| Grant date | Apr 5, 2005 |
| Priority date | — |
| Expiry date | Aug 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.