Nonvolatile semiconductor memory device having a memory cell that includes a floating gate electrode and control gate electrode
US6878985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Mar 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.