Word line arrangement having multi-layer word line segments for three-dimensional memory array
US6879505B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Apr 12, 2005 |
| Priority date | — |
| Expiry date | Apr 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) passive element memory cell array provides short word lines while still maintaining a small support circuit area for efficiency. Short, low resistance word line segments on two or more word line layers are connected together in parallel to form a given word line without use of segment switch devices between the word line segments. A shared vertical connection preferably connects the word line segments together and connects to a word line driver circuit disposed generally below the array near the word line. Each word line driver circuit preferably couples its word line either to an associated one of a plurality of selected bias lines or to an unselected bias line associated with the driver circuit, which selected bias lines are themselves decoded to provide for an efficient multi-headed word line decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.