Vertical flash memory cell with buried source rail
US6881628B2 · kind B2 · utility
7Cited by
7References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 25, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Sep 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A non-volatile memory cell has been described that includes source and drain regions that are fabricated on different horizontal planes. A floating gate and a control gate are fabricated vertically to control current conducted through the transistor. The control gate is coupled to a word line that is located above the transistor and traverses the memory in a direction perpendicular to the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.