Strained silicon NMOS devices with embedded source/drain
US6881635B1 · kind B1 · utility
102Cited by
24References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 23, 2004 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Mar 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planar NFET on a strained silicon layer supported by a SiGe layer achieves reduced external resistance by removing SiGe material outside the transistor body and below the strained silicon layer and replacing the removed material with epitaxial silicon, thereby providing lower resistance for the transistor electrodes and permitting better control over Arsenic diffusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.