Bonding pads for testing of a semiconductor device
US6882171B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jun 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/48139
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A first integrated circuit chip is provided for packaging along with at least a second integrated circuit chip in a semiconductor device, wherein at least some external terminals for the semiconductor device are to be shared by the first and the second integrated circuit chips, wherein the first integrated circuit chip is designed for normal operation and a test mode. The first integrated circuit chip includes up to eleven bonding pads for complete testing of the first integrated circuit chip, wherein the up to eleven bonding pads are for communicating TEST, SET, LOAD, and up to eight TDQ signals. The TEST, SET, and LOAD signals are operable to transition the first integrated circuit chip from normal operation into the test mode and to enable test codes to be loaded into the first integrated circuit chip during a programming phase of the test mode. The up to eight TDQ signals are operable to load test codes into the first integrated circuit during the programming phase of the test mode and to read/write data to and from the first integrated circuit chip during an access phase of the test mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.