Duty cycle corrector
US6882196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2002 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Jul 18, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.