Patent · US Expired

Integrated memory, and a method of operating an integrated memory

US6882554B2 · kind B2 · utility

5Cited by

6References

12Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Michael Markert · Augsburg, DE
Christian Weis · Scheidegg, DE
Sabine Kieser · Hausham, DE
Stefan Dietrich · Potsdam, DE
Peter Schrogmeier · Hersbruck, DE
Thomas Hein · Hersbruck, DE

Key dates

Filing date	Nov 4, 2002
Grant date	Apr 19, 2005
Priority date	—
Expiry date	May 23, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/105
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.