Reading ferroelectric memory cells
US6882560B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2003 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Oct 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A first fraction of a programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to other word lines coupled to control gates of non-selected memory cells. The first fraction of the programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells. A second fraction of the programming voltage is applied to a first bit line coupled to a second source/drain region of the selected memory cell and to other bit lines coupled to second source/drain regions of non-selected memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.