Method and program product for detecting bus conflict and floating bus conditions in circuit designs
US6883134B2 · kind B2 · utility
1Cited by
13References
76Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2001 |
| Grant date | Apr 19, 2005 |
| Priority date | — |
| Expiry date | Apr 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and program product for verifying a logic design for proper operation of tri-state buses in the design, comprises, for each bus in the circuit design, determining the smallest cut set, a min-cut, of the logic controlling the bus, performing an exhaustive analysis on a min-cut set of logic, and performing a full exhaustive analysis of the bus when the exhaustive analysis on the min-cut set of logic is inconclusive. In a preferred embodiment, prior to performing the min-cut set analysis, implication based conflict-free and float-free analyses are performed on the bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.