Vertical 8F2 cell dram with active area self-aligned to bit line

US6884676B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Norbert Arnold · Pfalzgrafenweiler, DE
• Venkatachalam C. Jaiprakash · Sunnyvale, US

Key dates

• Filing date: May 28, 2003
• Grant date: Apr 26, 2005
• Expiry date: May 28, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

A memory cell is formed in a memory cell array comprised of a plurality of memory cells arranged in rows and columns. A deep trench structure is formed within a semiconductor substrate and includes at least one conducting region. A patterned bit line structure is formed atop of, and electrically isolated from, the insulating region of the deep trench structure and atop of, but contacting at least part of, regions of the semiconductor substrate. Exposed portions of the semiconductor substrate are etched to form at least one isolation trench adjoining the deep trench structure using the patterned bit line structure as an etch mask. The isolation trench is filled with a dielectric material. A contact region to the conducting region of the deep trench structure is formed within the dielectric material of the isolation trench and is electrically isolated from the bit line structure. A word line structure that connects to the contact region is formed and is at least partly atop of, but electrically isolated from, the bit line structure.