Fabrication of self-aligned bipolar transistor
US6884689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2002 |
| Grant date | Apr 26, 2005 |
| Priority date | — |
| Expiry date | May 1, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
Abstract
A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.