Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6887769B2 · kind B2 · utility
455Cited by
42References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2002 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.