Dual damascene anti-fuse with via before wire
US6888215B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Apr 21, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse material formed on said substrate, wherein said patterned anti-fuse material includes an opening to at least one of said first level of electrically conductive features; a patterned interlevel dielectric material formed on said patterned anti-fuse material, wherein said patterned interlevel dielectric includes vias, as least one of said vias includes a via space; and a second level of electrically conductive features formed in said vias and via spaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.