Semiconductor power device with shear stress compensation
US6888246B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Jul 2, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.