Semiconductor memory device for improvement of defective data line relief rate
US6888775B2 · kind B2 · utility
2Cited by
2References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 5, 2003 |
| Grant date | May 3, 2005 |
| Priority date | — |
| Expiry date | Oct 30, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/848
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device according to the present invention includes: a data line switching circuit including a plurality of switches which selectively connect one of a plurality of normal data lines and spare data lines included in a memory cell array to one of a plurality of global data lines for transmitting input/output data to the memory cell array; and a switching control circuit including a shift decoder having decode circuits for decoding a defective address stored in a program circuit as many as the switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.