Methods for forming PN junction, one-time programmable read-only memory and fabricating processes thereof

US6890819B2 · kind B2 · utility

Assignee

• MACRONIX INTERNATIONAL CO., LTD. · TW

Inventors

• Chao-I Wu · Hsinchu, TW
• Ming-Hsiu Lee · Hsinchu, TW

Key dates

• Filing date: Sep 18, 2003
• Grant date: May 10, 2005
• Expiry date: Sep 18, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/25

Abstract

A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous silicon layer is filled into the opening, and then annealed to convert into a single-crystal silicon layer. Then, the dielectric layer is broken down to form a PN junction.